1. Field of the Invention
The present invention generally relates to a digital data converting method and the apparatus thereof and, more particularly, to a digital data converting method and apparatus thereof suitable for use with a case in which an audio signal or the like is pulse code-modulated (PCM) and then recorded.
2. Description of the Prior Art
If an analog signal such as an audio signal is converted to digital form prior to recording, the fidelity of the recorded signal thereof can be greatly enhanced. A common recording scheme converts an original analog signal into digital data using the pulse code modulation (PCM). The PCM digital data is then modulated using a so-called NRZI (non-return to zero, inverted) coding system. The NRZI coding system enables recording at the same bit densities possible with NRZ coding but without the problems associated with a signal polarity in the NRZ coding.
In the NRZI coding system, a "1" digital bit is represented by a transition between the two levels of a bi-level signal, while a continuation of the bi-level signal at the same level represents a "0" digital bit. In NRZI code, then, the actual level of the signal, whether high or low, does not represent digital information. Instead, the digital information is determined by whether or not the signal has changed levels between adjacent bit cells. For example, if the portion of the signal representing a particular bit of digital data is at the same level as the portion representing the preceding bit, then that particular bit is a digital zero.
The present applicant has previously proposed such information converting system as follows. This system employs a 8/10 converting scheme in which each eight bits of digital information in a base digital is converted to a ten-bit word to form a converted digital signal. Eight bits (B.sub.1, B.sub.2, B.sub.3, B.sub.4, B.sub.5, B.sub.6, B.sub.7, B.sub.8) can be combined in 256 (2.sup.8) different ways. With 10 bits, 1024 (2.sup.10) combinations are possible. Thus, 256 of the 1024 possible ten-bit combinations are used to represent the eight-bit combinations.
In accordance with the conditions set forth above, there are certain constraints on which 256 combinations can be used. First, those conditions require that the DC component in the converted signal be zero. Second, because NRZI coding is being used, the number of consecutive digital zeroes in the converted signal must never exceed three, otherwise T.sub.max /T.sub.min (where T.sub.max is the maximum interval between level transitions and T.sub.min is minimum interval between transitions) will be greater than four.
With those constraints, the following table I shows the possible combinations of ten digital bits in NRZI code for which the DC component is zero, but in which there are no more than three digital zeroes in a row (either internally of each ten-bit word or at the juncture between two such words):
TABLE I ______________________________________ . . . 1 . . . 10 . . . 100 . . . 1000 ______________________________________ 1 . . . 69 34 14 4 01 . . . 40 20 8 1 001 . . . 20 10 3 1 0001 . . . 8 3 2 1 ______________________________________
Table I shows that there are numerous possible combinations that will satisfy the constraints. For example, if up to three digital zeroes are permitted at the beginning of each word, then no digital zeroes can be permitted at the end of any word. In that case, Table I shows that the total of the possible combinations is: EQU 137=69+40+20+8
From all of the possible combinations in Table I, the maximum total is achieved if no more than two digital zeroes are permitted at the beginning of a ten-bit converted word and no more than one digital zero is permitted at the end. In that case, the total is: EQU 193=69+40+20+34+20+10
Thus, 193 ten-bit combinations are available for which the DC component is zero. These are called "primary combinations."
Since there are 256 possible eight-bit words of original data, 63 additional ten-bit combinations are required to represent all of the original data. Thus, it is necessary to use ten-bit combinations for which the DC component is not zero.
The following table illustrates the number of possible combinations of ten-bit combinations, which begin with no more than two digital zeroes and end with no more than one digital zero, having DC component with 0, -2 and +2 when NRZI-coded.
TABLE II ______________________________________ -2 0 +2 ______________________________________ 1 . . . 52 103 100 01 . . . 43 60 40 001 . . . 30 30 11 ______________________________________
Table II shows the 193 (=103+60+30) possible combinations in which the DC component is zero, as discussed in connection with Table II. Note that the entries in the "0" column of Table II: 103 (=69+34); 60 (=40+20); and 30 (=20+10), represent the totals from the " . . . 1" and " . . 01" columns of Table I.
To calculate the DC components for Table II it was assumed that the last bit of the next-preceding ten-bit combination was at the signal's low level. If Table II were constructed by assuming that the level of the last bit of the preceding word was high, then the "-2" and "+2" columns would be interchanged. In any case, the assumption regarding the beginning level of the converted words is merely a convention. The DC component obtained under that convention will be referred to as the "convention DC component". As will be clear below, it does not affect this case that the convention so established. That particular convention is adopted only for purposes of this description.
FIGS. 1A to 1C illustrate some examples of the converted words used to construct Table II. For example, FIGS. 1A and 1B show ten-bit combinations in NRZI code with a convention DC component of -2; FIG. 1C shows a ten-bit combination with a convention DC component of +2. FIGS. 1A to 1C also illustrate that if Table II were constructed defining the convention DC component by assuming the last bit of the next-preceding ten-bit combination was at the signal's higher level, the "-2" and "+2" columns would be reversed.
In any case, since only 193 primary ten-bit combinations, with a zero DC component, are available, 63 more "secondary combinations", those with a non-zero DC component are required to completely represent all of the 256 combinations possible with the original eight-bit data words. For reasons that are explained below, it is necessary in the above example that the initial bit of the ten-bit combination in NRZI code be a digital zero. In addition, in this embodiment the convention DC component of all of the secondary combinations is the same. That being the case, Table II shows that there are insufficient combinations (40+11) of bits having a convention DC component of +2. Thus, the required 63 additional combinations are chosen from the 73 (43+30) ten-bit combinations having a convention DC component of -2.
FIGS. 2A and 2B illustrate an important property of the ten-bit secondary combinations thus chosen. If the first bit in a secondary combination, as shown in FIG. 2B, is inverted, its convention DC component is changed from -2 to +2. It is possible to invert other bits within secondary combinations to change the DC component from -2 to +2, but it is preferred to change the convention DC component by inverting the first bit, since that always results in changing the DC component from -2 to +2 and changing the actual DC component from +2 or -2 to -2 or +2, respectively.
The method of this embodiment can be understood by reference to FIGS. 3A and 3B. Assume that, as shown in FIG. 3A, a particular portion of the converted digital signal ends at the lower signal level. Assume also that the DC component of the signal at the end of this signal portion is zero. In FIGS. 3A and 3B, the inverted delta indicates the beginning and end of consecutive converted words. If the first full converted word CW.sub.1 in FIG. 3A comprises a secondary combination, then its DC component will be -2. For all of the following words that comprise primary combinations, the DC components are zero. Thus, the DC component in the entire signal remains at -2. When the next secondary ten-bit combination CW.sub.3 is encountered, the DC component of the signal portion including the pair of secondary combinations can be returned to zero in accordance with this example by inverting a bit in the next secondary combination if its actual DC component is the same as the actual DC component of the first secondary combination in that signal portion.
Taking FIG. 3A as a first example, the number of level transitions in the signal portion including the pair of secondary combinations prior to the beginning of the second secondary combination is eight, which is an even number. The level of the signal at the beginning of the second secondary ten-bit combination will be the same after an even number of level changes as the signal level at the beginning of the first secondary combination. Thus, if the second secondary combination begins on the same level, its actual DC component will be the same, here a -2. But if the first bit of that second secondary combination is changed from a digital zero to a digital one, then the DC component of the second secondary combination becomes +2. When added to the actual DC component of the signal prior to the second secondary combination, which DC component was -2, the DC component of the entire signal portion is zero.
The reason that the first bit of the secondary combinations is chosen to be zero, as was pointed out above in connection with Table II, will now be clear. If secondary combinations were chosen with an initial bit of digital 1, then to change the actual DC component of that combination from -2 to +2, or vice versa, would require changing the first bit from a digital one to a digital zero. That change could result in having enough consecutive zeroes to make T.sub.max /T.sub.min greater than four.
In any case, FIG. 3B illustrates another example. If the number of level transitions before the start of the second secondary combination is odd, then that secondary combination begins at a high level and its DC component will be +2. Thus, no inversion is required to make the DC component of the entire three-word signal portion shown CW.sub.1 -CW.sub.3 in FIG. 3B zero.
FIG. 4 shows an example of an apparatus which is capable of conversion in accordance with the above system. In FIG. 4, reference numeral 1 designates an input terminal, 2 an 8-bit shift register which accepts information of 8 bits, 3 a conversion logic circuit and 4 a 10-bit shift register. Then, information applied to the input terminal 1 is transferred 8 bits by 8 bits through the shift register 2 and the information of 8 bits (B.sub.1, B.sub.2, B.sub.3, B.sub.4, B.sub.5, B.sub.6, B.sub.7, B.sub.8) is supplied to the logic circuit 3. In the logic circuit 3, the above one-to-one conversion is carried out and then information of converted 10 bits (P.sub.1, P.sub.2, P.sub.3, P.sub.4, P.sub.5, P.sub.6, P.sub.7, P.sub.8, P.sub.9, P.sub.10) is supplied to the shift register 4.
Further, the number of level transitions of the signal after being NRZI-coded is detected by the logic circuit 3. Since the number of level transitions is known in advance for each combination, a read-only memory, for example, which constructs the logic circuit 3 can simultaneously produce information regarding the number of level transitions (information is made enough to present only whether the number of level transitions is odd or even, and when it is odd, the information is digital "1".). This output Q is supplied to a latch circuit 8 and the latched output Q' from the latch circuit 8 is supplied to the logic circuit 3. A timing signal regarding information of every 8 bits supplied to the input terminal 1 is detected by a detecting circuit 9, and this timing signal is supplied to the load terminal of the shift register 4 and the latch terminal of latch circuit 8.
When the bits are converted to, for example, the above secondary combination, the latched output Q' is used in such a manner that when the latched output Q' is "0", the initial bit is converted to "1", while when the latched output Q' is "1", the initial bit is converted to "0". At that time, as the output Q is produced the information indicating whether the number of level transitions is odd or even which then is latched to the latch circuit 8. Further, when the bits are converted to the primary combination, the output of 10 bits is delivered as it is, and as the output Q is produced an odd or even information which is a sum between the number of level transitions of the primary combination and the latched output Q', which is then latched.
Further, a clock signal with frequency 5/4 times the clock of the input signal is supplied through a clock terminal 5 to the shift register 4 from which the above ten bits are read out in turn. This read-out signal is supplied to a JK flip-flop circuit 6 and the clock signal from the clock terminal 5 is supplied to the JK flip-flop circuit 6 so that a signal which is NRZI-coded is produced at an output terminal 7.
FIG. 5 shows an example of an apparatus for demodulating information which was modulated.
In FIG. 5, reference numeral 11 designates an input terminal through which a signal is supplied through an NRZI demodulating circuit 12 to a 10-bit shift register 13. Information of ten bits, P.sub.1 to P.sub.10 from the shift register 13 is supplied to a conversion logic circuit 14 in which the information of ten bits, P.sub.1 to P.sub.10 is demodulated using one-to-one reverse conversion. Accordingly, the demodulated information of eight bits, B.sub.1 to B.sub.8 is delivered to an 8-bit shift register 15 and then developed at an output terminal 16. In this case, when the above ten-bit information of the secondary combination is supplied to the logic circuit 14, the reverse conversion is carried out regardless of the initial bit.
As described above, the conversion and demodulation of data can be carried out.
In this system, however, when the logic circuits 3 and 14 are made of the read-only memory, a very large number of bits must be provided so that when the logic circuits 3 and 14 are formed as a large scale integrated circuit, a large area is required thereby, which then is not preferable.